Abstract: This lecture will cover the followings. (1) Formation of FOWLP: (a) Chip-First (Die Face-Down), (b) Chip-First (Die Face-Up), and (c) Chip-Last (or RDL-First). (2) Redistribution Layers (RDLs): (a) Polymer and ECD Cu + Etching, (b) PECVD and Cu Damascene + CMP, (c) Hybrid RDLs, and (d) Laser drill + LDI + PCB Cu-plating + Etching. (3) Formation of FOPLP: (a) Chip-First (Die Face-Down), (b) Chip-First (Die Face-Up), and (c) Chip-Last (or RDL-First). (4) TSMC InFO: (a) InFO-PoP, and (b) InFO_AiP Driven by 5G mmWave. (5) Samsung PLP: (a) PoP for Smart Watches and (b) SiP SbS for Smartphones. (6) Warpages: (a) Warpage Types and (b) Allowable of Warpages. (7) Reliability of FOWLP and FOPLP: (a) Thermal-Cycling Test, (b) Thermal-Cycling Simulations, (c) Drop Test, and (d) Drop Simulations. (8) Examples: (a) Chip-First Panel-Level Fan-Out Packaging of Mini-LED for RGB-Display, (b) Chip-Last Panel-Level Fan-Out Packaging of Application Processor Chipset, (c) 2.3D IC Integration with Chip-First Fan-Out RDL-Interposers, and (d) 2.3D IC Integration with Chip-Last Fan-Out RDL-Interposers. (9) Chiplet Design and HI Packaging vs. System-on-Chip (SoC). (10) Advantages and Disadvantages of Chiplet Design and HI Packaging. (11) Examples: (a) Xilinx Chiplet Design and HI Packaging (Virtex), (b) AMD Chiplet Design and HI Packaging (EPYZ and RYZEN), (c) Intel Chiplet Design and HI Packaging (FOVEROS, FOVEROS Direct, and Ponte Vecchio), and (d) TSMC Chiplet Design and HI Packaging (SoIC + CoWoS and SoIC + InFO PoP). (12) Chiplets Lateral Interconnects (Bridges): (a) Intel’s EMIB, (b) IBM’s DBHi, (c) Applied Materials’ Bridge Embedded in Fan-Out EMC, (d) SPIL’s FO-EB, (e) TSMC’s LSI, (f) ASE’s sFOCoS, (g) IME’s EFI, (h) Amkor’s S-Connect Fan-Out Interposer, and (i) UCIe. (13) Chiplet Design and HI Packaging on Organic Substrates (SiP): many examples. (14) Chiplet Design and HI Packaging on Silicon Substrates (TSV-Interposers): many examples: (a) Leti, (b) IME, (c) HKUST, (d) ITRI, (e) Xilinx/TSMC, (f) Altera/TSMC, (g) NVidia/TSMC, (h) AMD/UMC, (i) AMD’s Active Interposer, (j) Intel’s FOVEROS Direct and Ponte Vecchio, (k) TSMC’s SoIC, and (l) Samsung’s X-Cube and H-Cube. (15) Chiplet Design and HI Packaging on Fan-Out RDL Substrate for High Performance Applications: many examples: (a) STATSChipPac’s FOFC-eWLB, (b) ASE’s FOCoS (Chip-First), (c) MediaTek’s FO-RDLs, (d) TSMC’s InFO_oS and InFO_MS, (e) Samsung’s Si-Less RDL Interposer, (f) TSMC’s RDL-Interposer, (g) ASE’s FOCoS (Chip-Last), (h) Shinko’s Organic RDL-Interposer, and (i) Unimicron’s Hybrid Substrate. (16) Assembly Technologies for Chiplet Design and HI Packaging: (a) SMT, (b) Solder Bumped Flip Chip, (c) CoW, (d) WoW, (e) TCB, and (f) Bumpless Cu-Cu Hybrid Bonding.